PCB Design Basics

A PCB (Printed Circuit Board) turns a schematic into a physical product. Copper traces replace wires, component footprints replace breadboard holes, and ground planes replace the rat’s nest of ground wires. Getting the layout right determines whether a circuit works reliably or suffers from noise, thermal issues, and manufacturing defects.

Why It Matters

A perfect schematic can fail completely with bad PCB layout. Decoupling caps placed 2cm from the IC they protect are useless. Thin traces carrying high current melt. Missing ground planes create antenna loops that radiate EMI. PCB design is where theory meets manufacturing reality.

How It Works

Schematic to Layout Workflow

Schematic capture  →  Assign footprints  →  Generate netlist
       ↓
Component placement  →  Routing traces  →  Add copper fills
       ↓
Design Rule Check (DRC)  →  Fix violations  →  Generate Gerber files
       ↓
Send to fab house (JLCPCB, PCBWay, OSHPark)

Component Footprints

Every schematic symbol maps to a physical footprint (the copper pads on the PCB). Common formats:

Package	Size	Notes
0805	2.0 x 1.25mm	Good balance of size and hand-solderability
0603	1.6 x 0.8mm	Small, still hand-solderable with practice
0402	1.0 x 0.5mm	Requires reflow or hot air, hard to hand solder
SOT-23	2.9 x 1.3mm	Small transistors, regulators (3 pins)
SOIC-8	5.0 x 4.0mm	Op amps, small ICs, easy to solder
TQFP	varies	MCUs, large ICs (fine pitch, needs flux + patience)

Always verify the footprint matches the actual component datasheet. A wrong footprint means the board is scrap.

Trace Width for Current (IPC-2221)

Trace width determines how much current a trace can carry without excessive heating. Based on copper weight and acceptable temperature rise:

Current	Trace width (1oz Cu, 10C rise, outer layer)
0.5A	10 mil (0.25mm)
1A	20 mil (0.5mm)
2A	50 mil (1.27mm)
3A	80 mil (2.0mm)
5A	175 mil (4.4mm)

For power traces, use an online IPC-2221 calculator with your actual stackup. Inner layers carry less current than outer layers (worse thermal dissipation).

Signal traces (carrying mA) are typically 6-10 mil (0.15-0.25mm).

Ground Plane

The single most important PCB layout practice. Fill an entire copper layer with ground.

Benefits:

• Low-impedance return path for all signals (reduces EMI)
• Heat spreading
• Shielding
• Reference plane for controlled impedance traces (Signal Integrity)

Never break the ground plane under high-speed signals. If a signal trace crosses a gap in the ground plane, the return current must detour around the gap, creating a large loop antenna.

Decoupling Capacitor Placement

    WRONG:                      RIGHT:

    [IC]                        [IC]
      |                           |
      |  (long trace)           [100nF] ← within 3mm
      |                           |
    [100nF]                     Vcc plane / trace
      |
    Vcc trace

Rules:

1. 100nF ceramic within 3mm of each IC power pin (one per Vcc pin)
2. 10uF bulk cap within 20mm, shared among nearby ICs
3. Connect cap directly to the power pin and ground plane via short, wide traces or vias
4. Place on the same side as the IC when possible

See Capacitors and Inductors and Power Supply Design for sizing.

2-Layer vs 4-Layer Tradeoffs

	2-Layer	4-Layer
Cost	Low (~$5 for 5 boards)	2-3x more
Layer stackup	Top signal + bottom GND fill	Top signal / GND / Power / Bottom signal
Ground plane	Partial (shared with routing)	Dedicated, unbroken
EMI performance	Adequate below 10MHz	Good to 100MHz+
Impedance control	Difficult	Straightforward
Best for	Simple circuits, LED boards, breakouts	MCUs, wireless, USB, anything with fast edges

Start with 2-layer. Move to 4-layer when you need controlled impedance, better EMI, or cannot route everything on 2 layers.

Design Rule Check (DRC)

DRC catches violations before you send files to fabrication:

• Clearance: minimum spacing between copper features (typically 6mil/0.15mm)
• Trace width: minimum width (typically 6mil for standard fab)
• Via size: minimum drill and annular ring (0.3mm drill, 0.6mm pad typical)
• Silkscreen: text over pads, undersized labels
• Unconnected nets: signals that should connect but the router missed

Run DRC, fix every error, then run it again. Do not send boards with DRC violations.

Common Tools

Tool	Cost	Notes
KiCad	Free, open source	Professional quality, large community, cross-platform
EasyEDA	Free (web)	Integrated with JLCPCB parts library and ordering
Altium	Expensive	Industry standard, overkill for hobby/small projects
Eagle	Free tier	Legacy, acquired by Autodesk, KiCad is now preferred

KiCad is the recommended starting point. Its schematic editor, PCB layout tool, 3D viewer, and Gerber export cover everything you need.

Calculation Example

import math
 
# Trace width calculation (simplified IPC-2221 for outer layer, 1oz Cu)
i_target = 2.0        # amps
temp_rise = 10         # degrees C
thickness = 1.378      # mils (1 oz/ft^2 copper)
 
# IPC-2221 formula: A = (I / (k * dT^b))^(1/c)
# where A = cross-section area in mils^2
k, b, c = 0.048, 0.44, 0.725  # outer layer constants
area = (i_target / (k * temp_rise**b))**(1/c)  # mils^2
width_mils = area / thickness                    # ~50 mils for 2A
width_mm = width_mils * 0.0254                   # ~1.27 mm
 
# Via current capacity (rough rule: one standard via handles ~0.5A)
# For 2A, use 4 vias in parallel or one large via
vias_needed = math.ceil(i_target / 0.5)  # 4 vias
 
# Board area estimate: component count * average footprint area * 2
num_components = 30
avg_footprint_mm2 = 10  # ~0805 sized
board_area_mm2 = num_components * avg_footprint_mm2 * 2.5  # 750 mm2
# ~27mm x 27mm minimum, add margin -> 35x35mm practical

Related

• Signal Integrity — high-speed layout considerations
• Power Supply Design — regulator layout and decoupling
• Capacitors and Inductors — decoupling capacitor selection