Engineering Notes

Signal Integrity

5 min read

Signal Integrity

Signal integrity (SI) is the discipline of ensuring that electrical signals arrive at their destination undistorted. At low frequencies, wires are just wires. At high frequencies or with fast edges, every trace is a transmission line, every via is a discontinuity, and every ground plane gap is an antenna.

Why It Matters

A 100MHz clock signal with 1ns rise time has frequency content up to 350MHz. USB 2.0 runs at 480Mbps. SPI at 50MHz. Even a “slow” UART at 115200 baud is fine, but the MCU driving it may have 5ns edge rates containing harmonics above 100MHz. SI problems cause bit errors, EMI failures, and circuits that work on the bench but fail in production.

How It Works

Rise Time vs Bandwidth

The usable bandwidth of a digital signal is determined by its rise time, not its clock frequency:

BW = 0.35 / t_rise

A signal with 1ns rise time has 350MHz bandwidth. A 10ns rise time has 35MHz bandwidth. This is why slow protocols can still have SI issues if the driver has fast edges.

When to Worry About SI

The critical length rule: a trace acts as a transmission line when its length exceeds 1/10 of the signal wavelength.

Critical length = (propagation speed x rise time) / 10

For FR4 PCB: propagation ~ 15 cm/ns (roughly half speed of light)
Rise timeCritical lengthWorry if trace longer than
10ns150mm15mm (most board traces!)
5ns75mm7.5mm
1ns15mm1.5mm
0.3ns4.5mm0.45mm

Rule of thumb: if your signal has rise times below 5ns (most modern CMOS), any trace longer than ~50mm needs attention.

Transmission Line Effects

When a trace is electrically long, it has a characteristic impedance:

Z0 = sqrt(L_per_length / C_per_length)

For a microstrip trace over a ground plane, Z0 depends on trace width, dielectric height, and dielectric constant. Typical targets: 50 ohm single-ended, 90-100 ohm differential.

Impedance mismatch causes reflections. A signal hitting a mismatch bounces back, creating ringing and overshoot. The reflection coefficient:

rho = (Z_load - Z0) / (Z_load + Z0)

An open circuit (Z_load = infinity) reflects 100% of the signal. A matched load (Z_load = Z0) absorbs it all.

Impedance Matching and Termination

Series termination (most common for point-to-point):

    Driver ──[Rs]──── trace (Z0 = 50 ohm) ────── Receiver

    Rs = Z0 - Z_driver_output
    Typically 22-33 ohm for CMOS drivers

The signal leaves the driver at half amplitude, reaches the receiver at full amplitude (reflected wave adds constructively at the open receiver input). Simple, low power.

Parallel termination (for buses or when receiver must see full swing immediately):

    Driver ──── trace ────── Receiver
                              |
                            [Rt] = Z0
                              |
                             GND (or Vtt)

Consumes DC power (V^2/Rt) but ensures clean signal at the receiver.

Ground Bounce

When many outputs switch simultaneously, the current spike through the ground pin inductance creates a voltage bounce on the internal ground:

V_bounce = L_ground x dI/dt

With 1nH of ground pin inductance and 16 outputs switching 10mA each in 1ns:

V_bounce = 1e-9 x (16 x 10e-3 / 1e-9) = 0.16V

That is 160mV of noise on a 3.3V logic level — significant. Mitigations:

  • Multiple ground pins/vias (reduces inductance)
  • Decouple close to power pins (Capacitors and Inductors)
  • Stagger output switching (not all at once)
  • Use ICs with dedicated power/ground pin pairs

Crosstalk

Coupling between adjacent traces. Two mechanisms:

Capacitive crosstalk: electric field coupling between parallel traces. Dominant for high-impedance circuits and fast edges.

Inductive crosstalk: magnetic field coupling from current loops. Dominant for low-impedance, high-current circuits.

    Aggressor trace ═══════════════════
                      ↕ coupling region
    Victim trace    ═══════════════════

Reduce crosstalk:

  • Increase trace spacing (3x trace width minimum for sensitive signals)
  • Reduce parallel run length
  • Use ground plane (provides nearby return path, reduces loop area)
  • Route sensitive signals on adjacent layers with perpendicular orientation

Practical: When to Worry

SituationSI concern?Action
UART at 115200 baudNoJust route it
I2C at 400kHzNoPull-up resistors per spec, that’s it
SPI at 1MHzNoShort traces, bypass caps, done
SPI at 50MHzYesSeries termination, short traces, ground plane
USB 2.0 (480Mbps)Yes90 ohm differential, controlled impedance, length matching
Ethernet (100BASE-TX)YesDifferential pairs, magnetics, follow reference layout
DDR3/4 memoryVery yes4-layer minimum, impedance control, length matching, simulation
HDMI / PCIeVery yesControlled impedance, via stitching, S-parameter modeling

Calculation Example

import math
 
# Rise time to bandwidth
t_rise = 2e-9  # 2ns (typical for 3.3V CMOS)
bw = 0.35 / t_rise  # 175 MHz
 
# Critical trace length (FR4)
v_prop = 0.15  # m/ns (half speed of light in FR4)
critical_length_m = v_prop * t_rise * 1e9 / 10  # 0.03m = 30mm
# Traces longer than 30mm need controlled impedance at 2ns rise time
 
# Microstrip impedance (approximate formula)
# Z0 = 87 / sqrt(er+1.41) * ln(5.98*h / (0.8*w + t))
# where h=dielectric height, w=trace width, t=copper thickness, er=dielectric const
er = 4.4      # FR4
h = 0.2       # mm (distance to ground plane, typical 4-layer)
w = 0.3       # mm (trace width)
t = 0.035     # mm (1oz copper)
z0 = (87 / math.sqrt(er + 1.41)) * math.log(5.98 * h / (0.8 * w + t))
# ~50 ohm (adjust w to hit your target)
 
# Ground bounce
l_pin = 1e-9       # 1 nH ground pin inductance
n_outputs = 8
i_per_output = 10e-3  # 10 mA
t_switch = 2e-9     # 2 ns
v_bounce = l_pin * (n_outputs * i_per_output) / t_switch  # 40 mV

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